Scoreboards and reference models

Predicting what the DUT should do and comparing it with what it did, in order or out of order.

• The scoreboard that fails a perfect DUT (Object comparison · Easy · about 10 min)
• The scoreboard that writes whole words (Memory models · Easy · about 10 min)
• The reference model that rotates by too much (Reference models · Easy · about 10 min)
• A scoreboard that never notices missing data (Scoreboards · Easy · about 10 min)
• A scoreboard for out-of-order responses (Scoreboards · Medium · about 15 min)
• The scoreboard that never stalls (Reference models · Medium · about 15 min)
• The mirror that believes every write (Register models · Medium · about 15 min)
• The scoreboard that believes a FIFO is bottomless (FIFO models · Medium · about 15 min)

Posedge Daily posts two hardware interview questions every day at midnight Eastern: one RTL design question and one verification question. You write SystemVerilog in the browser, run it on Verilator or Icarus Verilog, read the waveform, and see which hidden tests pass. It covers SVA, constrained random and UVM, and it is free.