Practice by topic

Every released RTL design and verification question, grouped by topic, easiest first.

State machines

Rising-edge pulse detector (Design · Easy · about 10 min)
Overlapping 1011 detector (FSMs · Easy · about 10 min)
A debouncer that adds up the bounces (Counters · Easy · about 10 min)
A timer that restarts when poked (Timers · Easy · about 10 min)
A remainder tracker that drops the first bit (Remainder FSMs · Easy · about 10 min)
A run detector that pulses on every bit after the third (Run detection · Easy · about 10 min)
A one-hot FSM that resets into limbo (One-hot FSMs · Easy · about 10 min)
A receiver that needs a breather between bytes (Serial receivers · Medium · about 15 min)
A serial negator that trips over the first bit (Serial arithmetic · Medium · about 12 min)
Serial transmitter that forgets its byte (Serial transmitters · Medium · about 15 min)

Datapath and arithmetic

An LFSR that repeats too soon (LFSRs · Easy · about 10 min)
A saturating adder that clamps at the wrong time (Arithmetic · Easy · about 10 min)
A Gray counter that changes two bits (Gray code · Easy · about 10 min)
Lowest request wins (Priority encoders · Easy · about 10 min)
A counter that counts when asked to do both (Up/down counters · Easy · about 10 min)
A parity checker that blames the next frame (Parity · Easy · about 10 min)
A priority encoder that favors the wrong end (Priority encoders · Easy · about 10 min)
A CRC that needs eight more bits (CRC · Medium · about 15 min)
A shifter that loses the sign (Shifters · Medium · about 10 min)
Hamming(7,4) decoder (ECC · Medium · about 15 min)
Sequence numbers that don't know the counter wraps (Wraparound compare · Medium · about 12 min)

Handshakes and flow control

A packet marker that counts stalled beats (Beat counting · Easy · about 10 min)
A width converter that skips a beat under backpressure (Width conversion · Easy · about 10 min)
A six-slot FIFO whose pointers walk off the end (Ring buffers · Easy · about 10 min)
An almost-full flag that warns one entry too late (Almost-full · Easy · about 10 min)
A credit counter that leaks credits (Flow control · Medium · about 15 min)
A pipeline that overwrites a stalled result (Pipeline stalls · Medium · about 15 min)
A fork that delivers the same beat twice (Stream forks · Medium · about 15 min)
A depth-4 FIFO that counts to 5 (Waveform debug · Hard · about 15 min)
A skid buffer that drops a beat (Handshakes · Hard · about 20 min)

Clocks, resets and CDC

Asynchronous and synchronous resets (Resets · Easy · about 10 min)
A tick that comes one cycle late (Clock dividers · Easy · about 10 min)
A reset stretcher that only stretches once (Reset stretching · Easy · about 10 min)
A divided clock that's only high for one cycle (Duty cycle · Easy · about 10 min)
A counter that skips across clocks (Clock crossing · Medium · about 15 min)
A pulse that falls between two clock edges (Synchronizers · Medium · about 15 min)
Reset: assert fast, release in step (Reset synchronizers · Medium · about 15 min)
A clock gate that makes runt pulses (Clock gating · Medium · about 15 min)

Arbiters and memory structures

A register file that's one write behind (Register files · Easy · about 10 min)
A CAM that finds keys nobody stored (CAMs · Easy · about 10 min)
A round-robin arbiter that plays favorites (Arbitration · Medium · about 15 min)
An LRU tracker that forgets the oldest way (Caches · Medium · about 15 min)
A stack that loses count (Stacks · Medium · about 15 min)
A pseudo-LRU tree that forgets the other half (LRU tracking · Medium · about 15 min)
An allocator that says full one cycle too long (Free lists · Medium · about 15 min)
A bus lock that outlasts the packet (Packet arbitration · Medium · about 15 min)

Assertions (SVA)

The assertion that checks the wrong cycle (Assertions · Easy · about 10 min)
The assertion that fails once every 256 counts (Sampled values · Easy · about 10 min)
The assertion that accepts a busy that never ends (Sequences · Easy · about 10 min)
The assertion that blames the cycle after the lock (Stability · Easy · about 10 min)
Catch the late acknowledge (Assertions · Medium · about 15 min)
The assertion that watches one line out of four (Edge functions · Medium · about 15 min)
The grant checker that fires on an idle bus (Assertions · Medium · about 15 min)
The assertion that compares with the wrong request (Delayed checks · Medium · about 10 min)
The assertion that stops checking one cycle early (Until and throughout · Medium · about 12 min)

Constraints and randomization

Weighting a random length (Constraints · Easy · about 10 min)
The checksum that's one packet behind (Randomization · Easy · about 10 min)
The header that never changes (Nested objects · Easy · about 10 min)
Four tags, all different (Unique constraints · Easy · about 10 min)
Tags that repeat before the round is over (randc · Easy · about 10 min)
The check byte that belongs to the last frame (post_randomize · Easy · about 10 min)
Weighted burst lengths (Distributions · Easy · about 10 min)
The pinned address that pins everything (rand_mode · Easy · about 10 min)
The burst that runs off the end of memory (Constraints · Medium · about 15 min)
The inline constraint that constrains nothing (Inline constraints · Medium · about 15 min)
The flag that's never set (solve before · Medium · about 12 min)

Scoreboards and reference models

The scoreboard that fails a perfect DUT (Object comparison · Easy · about 10 min)
The scoreboard that writes whole words (Memory models · Easy · about 10 min)
The reference model that rotates by too much (Reference models · Easy · about 10 min)
A scoreboard that never notices missing data (Scoreboards · Easy · about 10 min)
A scoreboard for out-of-order responses (Scoreboards · Medium · about 15 min)
The scoreboard that never stalls (Reference models · Medium · about 15 min)
The mirror that believes every write (Register models · Medium · about 15 min)
The scoreboard that believes a FIFO is bottomless (FIFO models · Medium · about 15 min)

Processes and synchronization

The racy driver (Testbench races · Easy · about 10 min)
The timeout that outlives its wait (Processes · Medium · about 15 min)
The lock that's given back too soon (Semaphores · Medium · about 15 min)
Five packets in the mailbox, all the same one (Mailboxes · Medium · about 10 min)
The test that ends with items still queued (End of test · Medium · about 12 min)
Workers that all think they are the last one (Fork in loops · Medium · about 15 min)
The signal that nobody was waiting for (Events · Medium · about 12 min)
The producer that drops items when the mailbox is full (Bounded mailboxes · Medium · about 15 min)

Classes and data structures

The flush that leaves some behind (Queues · Easy · about 10 min)
The tag that never reaches the wire (Polymorphism · Easy · about 10 min)
Every packet is packet number 0 (Static members · Easy · about 10 min)
The histogram walk that skips the first address (Associative arrays · Easy · about 10 min)
The helper that drains a copy (Argument passing · Easy · about 10 min)
The cast that keeps the last write (Casting · Easy · about 10 min)
The constructor that assigns a field to itself (Constructors · Easy · about 10 min)
The copy that shares its header (Classes · Medium · about 15 min)

UVM

The driver that ignores ready (UVM · Medium · about 15 min)
The test that ends at time 0 (UVM · Medium · about 15 min)

Posedge Daily posts two hardware interview questions every day at midnight Eastern: one RTL design question and one verification question. You write SystemVerilog in the browser, run it on Verilator or Icarus Verilog, read the waveform, and see which hidden tests pass. It covers SVA, constrained random and UVM, and it is free.