RTL Design #19 · 2026-10-12 · Clock dividers · Easy · about 10 min

A tick that comes one cycle late

tick_gen divides the clock down to a slower beat: tick is a registered output that is high for one cycle in every period cycles.

• Count the rising edges since the last tick, or since reset. On the edge that makes the count reach period, tick goes high for one cycle and the count starts again. So after reset with period = 4, tick goes high on the 4th edge, the 8th, the 12th, …
• period is 1 to 255. With period = 1, tick stays high.
• period may change at any time. Only the count matters: if it has already reached or passed the new period, tick goes high on the very next edge.
• Reset is synchronous: it clears the count and tick.

Run asks for a tick every 4 cycles and then changes the period twice. The ticks don't come when they should. Fix tick_gen.sv.

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