Verification #22 · 2026-10-15 · Edge functions · Medium · about 15 min

The assertion that watches one line out of four

An interrupt controller has four interrupt lines, irq[3:0], and a pending bit for each, pend[3:0]. One rule ties them together, separately for each line i:

• When irq[i] rises (0 at one clock edge, 1 at the next), pend[i] must be 1 in the cycle after the rise.

Nothing else is required. Software clears pending bits whenever it likes, even while the line is still high, and several lines can rise in the same cycle or while others are already high.

checker.sv is meant to count in fails each time a pending bit isn't set when the rule says it must be, and nothing while rst_n is low. It misses most of the real mistakes, and now and then it reports one that isn't there. Fix it. Keep fails++ in the failure branch: the testbenches read it.

The controller in testbench.sv makes exactly one mistake.

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