RTL Design #46 · 2026-11-08 · One-hot FSMs · Easy · about 10 min

A one-hot FSM that resets into limbo

seq is a small sequencer with three one-hot states: IDLE, RUN and DONE. Exactly one bit of state is meant to be set at a time, and the next-state logic is a one-hot reverse case (case (1'b1)).

• IDLE → RUN when start is high.
• RUN holds until finish is high, then → DONE. busy is high for every cycle in RUN.
• DONE → IDLE the next cycle. done pulses for that single cycle.
• rst_n (synchronous, active low) returns the sequencer to IDLE.

Out of reset, start never seems to do anything: busy and done stay low forever. Fix seq.sv.

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