RTL Design #41 · 2026-11-03 · Ring buffers · Easy · about 10 min

A six-slot FIFO whose pointers walk off the end

ring_fifo in ring.sv is a synchronous FIFO with DEPTH = 6, stored in a ring of six slots. The first fill and drain work, but after that the data coming out is wrong.

It must behave like a 6-entry FIFO: a write is accepted only while full is 0, a read only while empty is 0, full and empty match what is stored on every cycle, and rdata is valid the cycle after a read. Fix ring.sv.

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