RTL Design #44 · 2026-11-06 · Duty cycle · Easy · about 10 min

A divided clock that's only high for one cycle

clkdiv divides clk down to a slower clock on clk_out. Given half (the number of input cycles in each half period, at least 1), clk_out is a 50% duty clock:

• it is high for half cycles, then low for half cycles, and so on — a divide-by-2*half clock;
• out of synchronous reset it starts low, counting from 0.

The current version pulses clk_out high for a single cycle at the end of each half period instead of holding it. Fix clkdiv.sv so clk_out is a proper square wave.

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