RTL Design #16 · 2026-10-09 · Synchronizers · Medium · about 15 min

A pulse that falls between two clock edges

pulse_sync carries events from clk_a to the unrelated clk_b domain. Each event is a one-cycle pulse on pulse_a, and must come out as exactly one one-cycle pulse on pulse_b, within 6 clk_b cycles.

• clk_b may be faster than clk_a or many times slower. The design can't assume either.
• The sender leaves at least 8 cycles of both clocks between two pulses.
• Only a two-flop synchronizer clocked by clk_b may sample a signal from clk_a, and that signal must come straight from a clk_a flop.

The design in design.sv works when clk_b is the faster clock. Run uses a slower clk_b and counts the pulses on each side.

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