Clocks, resets and CDC

Synchronous and asynchronous resets, and getting values safely from one clock domain to another.

• Asynchronous and synchronous resets (Resets · Easy · about 10 min)
• A tick that comes one cycle late (Clock dividers · Easy · about 10 min)
• A reset stretcher that only stretches once (Reset stretching · Easy · about 10 min)
• A divided clock that's only high for one cycle (Duty cycle · Easy · about 10 min)
• A counter that skips across clocks (Clock crossing · Medium · about 15 min)
• A pulse that falls between two clock edges (Synchronizers · Medium · about 15 min)
• Reset: assert fast, release in step (Reset synchronizers · Medium · about 15 min)
• A clock gate that makes runt pulses (Clock gating · Medium · about 15 min)

Posedge Daily posts two hardware interview questions every day at midnight Eastern: one RTL design question and one verification question. You write SystemVerilog in the browser, run it on Verilator or Icarus Verilog, read the waveform, and see which hidden tests pass. It covers SVA, constrained random and UVM, and it is free.