Verification #18 · 2026-10-11 · Sampled values · Easy · about 10 min

The assertion that fails once every 256 counts

An 8-bit counter has an enable. On every rising clock edge:

1. if en is 1, count in the next cycle is one more than it is now, and FF is followed by 00;
2. if en is 0, count in the next cycle is the same as it is now.

checker.sv is meant to catch counters that break these rules, counting in fails one failure for each clock edge at which count isn't what the rules say, and nothing while rst_n is low. It does catch them, but it also reports failures on a counter that does nothing wrong. Fix it, without letting any real mistake through. Keep fails++ in the failure branches: the testbenches read it.

The counter in testbench.sv makes exactly one mistake.

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