Handles, copies, queues and associative arrays: SystemVerilog's object and container semantics.
Posedge Daily posts two hardware interview questions every day at midnight Eastern: one RTL design question and one verification question. You write SystemVerilog in the browser, run it on Verilator or Icarus Verilog, read the waveform, and see which hidden tests pass. It covers SVA, constrained random and UVM, and it is free.