Verification #38 · 2026-10-31 · Stability · Easy · about 10 min

The assertion that blames the cycle after the lock

A bus has a lock signal and a 4-bit addr. One rule ties them together:

• In any cycle where lock is 1 and was also 1 in the cycle before, addr must equal its value in the cycle before.

Nothing else is required. The master may set a new address in the very cycle it takes the lock, and in the cycle it releases it. The lock may also be held for a single cycle.

checker.sv is meant to count in fails each cycle that breaks the rule, and nothing while rst_n is low. It reports mistakes that aren't there. Fix it. Keep fails++ in the failure branch: the testbenches read it.

The bus in testbench.sv makes exactly one mistake.

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