RTL Design #17 · 2026-10-10 · Register files · Easy · about 10 min

A register file that's one write behind

regfile holds eight 8-bit registers for a small CPU. It has one write port and two read ports:

• A write happens on the rising edge when we is 1: register waddr takes wdata.
• Both reads are combinational: rdata_a and rdata_b show registers raddr_a and raddr_b.
• Register 0 always reads as zero, and writes to it are ignored.
• A read of the register that is being written in the same cycle returns the new wdata, not the value about to be replaced.

The last rule is there for the pipeline: writeback and decode overlap, and an instruction in decode must see the result that writeback is storing this cycle. The current design gives it the old value instead. Fix regfile.sv.

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