RTL Design #21 · 2026-10-14 · Pipeline stalls · Medium · about 15 min

A pipeline that overwrites a stalled result

pipe_add adds three bytes in two pipeline stages, with valid/ready on both sides. A beat moves when valid and ready are both 1 at a rising edge. Stage 1 holds a + b and c, and stage 2 holds the result a + b + c (8 bits, wrapping).

• Every beat that goes in comes out exactly once, in order, with the sum of its own a, b and c.
• While out_valid is 1 and out_ready is 0, out_valid and out_data hold.
• A stage takes a new beat whenever it's empty or its own beat is moving on. So in_ready is 0 only when both stages hold a beat and out_ready is 0, and with in_valid and out_ready held at 1 one beat goes through every cycle.
• After reset both stages are empty.

With the consumer always ready the current design works. When it stalls, sums go wrong. Fix pipe_add.sv.

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