RTL Design #23 · 2026-10-16 · Serial arithmetic · Medium · about 12 min

A serial negator that trips over the first bit

serial_neg negates numbers that arrive one bit per clock, least significant bit first: for each word in, the two's complement comes out on dout, bit for bit, in the same cycle as the din bit it answers.

• start is 1 together with the first (least significant) bit of every word. Words are any length and follow each other with no gap, so the bit after a word's last is the next word's first.
• The rule for negating serially: copy the bits up to and including the first 1, and invert every bit after it.
• The first bit after reset always has start = 1.

The current FSM gets some words right and others wrong. Fix negate.sv.

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