RTL Design #25 · 2026-10-18 · Reset synchronizers · Medium · about 15 min

Reset: assert fast, release in step

reset_sync turns a reset that can change at any moment (arst_n, active low) into one that is safe to use in the clk domain. It has two jobs:

• Assert at once. When arst_n falls, rst_n_out falls with it, without waiting for a clock edge.
• Release in step with the clock. After arst_n rises, rst_n_out stays low through the first rising edge of clk and rises on the second one, so that a flop in the domain never sees the reset go away right at its clock edge.

The current design.sv does neither. Fix it.

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