RTL Design #37 · 2026-10-30 · Clock gating · Medium · about 15 min

A clock gate that makes runt pulses

clk_gate is a latch-based clock gate: gclk is clk when en is 1 and stays low when en is 0.

• en may change at any time, including in the middle of a high phase of clk. gclk must never produce a runt pulse (a pulse shorter than the high phase of clk) and must never be cut short.
• A pulse is whole or it isn't there. The value of en that counts for a rising edge of clk is the one it had when clk was last low. A change of en while clk is high only takes effect from the next rising edge.
• en is a plain input: don't register it with a flip-flop, which would delay it by a whole cycle.

Run drops en in the middle of a pulse and raises it in the middle of a high phase. Fix clk_gate.sv.

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