Verification #4 · 2026-09-27 · Testbench races · Easy · about 10 min

The racy driver

Tests drive the DUT through bus.drive(v) in driver.sv, often straight after @(posedge clk). The DUT is one flop, always_ff @(posedge clk) q <= din;, and it should sample each value on the next rising edge after the call.

The current driver passes on Icarus. On Verilator, every value driven at an edge lands one cycle early, and tests that check the DUT fail for no fault of the DUT.

Fix drive() so every value lands on the next rising edge after the call, wherever in the cycle it's called, on both simulators.

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