Verification #14 · 2026-10-07 · Assertions · Easy · about 10 min

The assertion that checks the wrong cycle

On a valid/ready link, a beat is transferred on a rising clock edge where valid and ready are both 1. A sender that is offering a beat the receiver hasn't taken yet (valid = 1, ready = 0) has to wait, and on the next cycle:

1. valid must still be 1, and
2. data must be the same.

Once the beat is transferred the sender is free: it may drop valid, or offer a new beat with new data on the very next cycle.

checker.sv is meant to catch senders that break these rules, counting in fails one failure for each clock edge where a waiting beat was withdrawn or changed, and nothing while rst_n is low. The current assertion fires on legal traffic and misses real violations. Fix it. Keep fails++ in the failure branch: the testbenches read it.

The stimulus in testbench.sv breaks the rules exactly twice.

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