Verification #17 · 2026-10-10 · Register models · Medium · about 15 min

The mirror that believes every write

The DUT has one 8-bit STATUS register with three fields:

Bits	Field	Behavior
`[7:6]`	`ver`	Read-only, always `2'b10`. Writes don't change it.
`[5:4]`	`irq`	Hardware sets a bit when its event happens. Writing 1 to a bit clears it, and writing 0 leaves it alone.
`[3:0]`	`ctrl`	Read/write: holds the last value written.

It resets to 8'h80.

reg_model in reg_model.sv is the testbench's copy of that register. The monitors call write(wdata) for every bus write, hw_event(ev) when hardware raises the irq bits that are 1 in ev, and reset() on reset. When a write and an event land in the same cycle, write() is called first, so a bit raised in the cycle it's cleared stays set. The scoreboard compares mirror with every bus read.

The current model reports mismatches against a DUT that is correct. Fix reg_model.sv so that mirror always holds what the register holds.

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